Substrates that include one or more layers of semiconductor material are used to form a wide variety of semiconductor structures and devices including, for example, integrated circuit (IC) devices (e.g., logic processors and memory devices) and discrete devices such as, radiation emitting devices (e.g., light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity surface emitting lasers (VCSELs)), and radiation sensing devices (e.g., optical sensors). Such semiconductor devices are conventionally formed in a layer-by-layer manner (i.e., lithographically) on and/or in a surface of a semiconductor substrate.
Historically, a majority of such semiconductor substrates that have been used in the semiconductor device manufacturing industry have comprised thin discs or “wafers” of silicon material. Such wafers of silicon material are fabricated by first forming a large generally cylindrical silicon single crystal ingot and subsequently slicing the single crystal ingot perpendicularly to its longitudinal axis to form a plurality of silicon wafers. Such silicon wafers may have diameters as large as about thirty centimeters (30 cm) or more (about twelve inches (12 in) or more). Although silicon wafers generally have thicknesses of several hundred microns (e.g., about 700 microns) or more, only a very thin layer (e.g., less than about three hundred nanometers (300 nm)) of the semiconductor material on a major surface of the silicon wafer is generally used to form active devices on the silicon wafer. However, in some device applications the majority of the silicon wafer thickness may be included in the electrical path-way of one or more device structures formed from the silicon wafer, such device structures being commonly referred to as “vertical” device structures.
So-called “engineered substrates” have been developed that include a relatively thin layer of semiconductor material (e.g., a layer having a thickness of less than about three hundred nanometers (300 nm)) disposed on a layer of dielectric material (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3)). Optionally, the layer of dielectric material may be relatively thin (e.g., too thin to enable handling by conventional semiconductor device manufacturing equipment), and the semiconductor material and the layer of dielectric material may be disposed on a relatively thicker host or base substrate to facilitate handling of the overall engineered substrate by manufacturing equipment. As a result, the base substrate is often referred to in the art as a “handle” or “handling” substrate. The base substrate may also comprise a semiconductor material other than silicon.
A wide variety of engineered substrates are known in the art and may include semiconductor materials such as, for example, silicon (Si), germanium (Ge), III-V type semiconductor materials, and II-VI type semiconductor materials.
For example, an engineered substrate may include an epitaxial layer of III-V type semiconductor material formed on a surface of a base substrate, such as, for example, aluminum oxide (Al2O3) (which may be referred to as “sapphire”). The epitaxial layer may be formed on the surface of the base substrate by a transfer process from a donor structure, for example a donor substrate or donor ingot. The transfer from a donor structure may be desirable when the donor material is highly valuable or in scarce supply. Using such an engineered substrate, additional layers of material may be formed and processed (e.g., patterned) over the epitaxial layer of III-V type semiconductor material to form one or more devices on the engineered substrate. However, the coefficient of thermal expansion mismatch (or difference) between the epitaxial layer and the base substrate comprising the engineered substrate, may influence the formation and processing of the additional layers of material. For example, if the coefficient of thermal expansion mismatch between the epitaxial layer and the base substrate is substantial then the engineered substrate may be negatively impacted during the formation of additional layers of materials.
Examples of devices that can take advantage of engineered substrates are high power devices and photonic devices, such as, Light Emitting Diodes (LEDs) and laser diodes. FIG. 1 illustrates a conventional LED. A substrate 110, which may be an engineered substrate, includes an n-type layer 120 disposed thereon. An active region 130, which may include multiple layers, such as, for example, quantum wells, barrier layers, electron blocking layer(s) (EBL) etc., is disposed between the n-type layer 120 and a p-type layer 140. The result is an LED formed by the n-type layer 120, the active region 130, and the p-type layer 140. A first contact 160 provides an electrical connection to the n-type layer 120 and a second contact 150 provides another electrical connection to the to the p-type layer 140. These contacts may be opaque to the wavelength of light emitted by the LED and, as a result, may diminish the overall amount of light available from the LED. Thus, only the area between the first contact 160 and the second contact 150 may produce significant amounts of light. The physical layout of the second contact 150 relative to the n-type layer 120 may cause current crowding in the current flowing between the p-type layer 140 and the n-type layer 120. In addition, the physical layout may require that both p and n-type contacts are disposed on an upper surface of the LED structure, wherein such a physical layout may require removal of a portion of the device layers to expose regions for contacting. The removal of a portion of the device layers may increase the complexity of device fabrication, may reduce the area available for light generation and may also decrease device yield.
In view of the above, and for other reasons discussed below, there is a need for a substrate technology that provides a suitable base substrate for donated material from a donor structure. Moreover, there is a need for devices and methods that provide a support substrate with a closely matching Coefficient of Thermal Expansion (CTE) with that of an engineered substrate.